Company:Qualcomm India Private Limited

Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Key Responsibilities

Own end‑to‑end functional verification of complex IPs/cores from specification to tape‑out, with deep understanding of RTL.Architect, develop, and execute SystemVerilog/UVM‑based testbenches and verification plans aligned to design specifications and coverage goals.Drive coverage‑driven verification (functional, code, and assertion coverage) and lead coverage closure and sign‑offAct as the primary debug owner, analyzing failures across RTL, testbench, assertions, and regressions using waveforms, logs, and coverage data; optimize build, simulation, and regression performanceApply industry‑standard verification methodologies and advanced AI/ML‑based DV techniques to improve stimulus generation, target coverage gaps, accelerate debug, and reduce verification cycle time while collaborating closely with design and EDA teams.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Required Skills & Experience

5+ years of experience in IP verification for ASIC designs.Strong expertise in System Verilog, SVA, UVM, and Verilog.Solid understanding of ASIC design flow and design fundamentals.Proven experience in testbench architecture, testbench development, test plan creation, and coverage analysis.Hands-on experience with latest debug tools and methodologies.Knowledge of AI/ML concepts and their application in verification is a strong plus.Excellent communication, problem-solving, and documentation skills.Protocols – AHB, APB, AXI is a strong plus.

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