Role Summary:
Assist the STA team in checking timing quality of chip designs to make sure signals arrive at the right time and the chip works at the intended speed.
Key Responsibilities:
Support timing analysis of digital circuits using STA tools
Run timing checks like setup, hold, and clock skew
Work with synthesis, placement & routing teams to fix timing issues
Learn STA tools (e.g., PrimeTime, Tempus) and scripting (e.g., TCL, Perl)
Document timing reports and assist in analysis reviews
Skills
Basics of timing concepts: setup, hold, clock tree
STA tools (PrimeTime, etc.)
Scripting languages (TCL, Shell)
Chip design flow from RTL to GDSII
Work Experience
Skills
Basics of timing concepts: setup, hold, clock tree
STA tools (PrimeTime, etc.)
Scripting languages (TCL, Shell)
Chip design flow from RTL to GDSII