Tech Lead - Physical Design
QuEST Global
Job Requirements
Key Responsibilities:Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems.Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies.Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance.Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges.Run power optimization techniques at synthesis and post-route stage.Support subsystem-level integration and participate in debug and convergence discussions.Write scripts (Python, Tcl) for flow automation, data mining, and report generation.Required Skills:Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus.Working knowledge of low power flows, UPF, VCLP, power intent checks.Familiarity with timing closure concepts, signal integrity, and power optimization.Good scripting skills in Python/Tcl/Perl for design automation.Enthusiastic team player with strong analytical and debugging skills.
Work Experience
Key Responsibilities:Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems.Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies.Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance.Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges.Run power optimization techniques at synthesis and post-route stage.Support subsystem-level integration and participate in debug and convergence discussions.Write scripts (Python, Tcl) for flow automation, data mining, and report generation.Required Skills:Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus.Working knowledge of low power flows, UPF, VCLP, power intent checks.Familiarity with timing closure concepts, signal integrity, and power optimization.Good scripting skills in Python/Tcl/Perl for design automation.Enthusiastic team player with strong analytical and debugging skills.
Key Responsibilities:Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems.Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies.Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance.Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges.Run power optimization techniques at synthesis and post-route stage.Support subsystem-level integration and participate in debug and convergence discussions.Write scripts (Python, Tcl) for flow automation, data mining, and report generation.Required Skills:Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus.Working knowledge of low power flows, UPF, VCLP, power intent checks.Familiarity with timing closure concepts, signal integrity, and power optimization.Good scripting skills in Python/Tcl/Perl for design automation.Enthusiastic team player with strong analytical and debugging skills.
Work Experience
Key Responsibilities:Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems.Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies.Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance.Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges.Run power optimization techniques at synthesis and post-route stage.Support subsystem-level integration and participate in debug and convergence discussions.Write scripts (Python, Tcl) for flow automation, data mining, and report generation.Required Skills:Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus.Working knowledge of low power flows, UPF, VCLP, power intent checks.Familiarity with timing closure concepts, signal integrity, and power optimization.Good scripting skills in Python/Tcl/Perl for design automation.Enthusiastic team player with strong analytical and debugging skills.
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