The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.

Work hard. Have fun. Make history.

Roles & Responsibilities:
- Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge & Low power SOCs.
- Perform I/O, bump & RDL (redistribution layer) planning, hard IP integration, partitioning, pin and feedthrough planning, repeater insertion, power grid generation.
- Perform special interface, and interconnect planning, bus routing, sequential pipeline planning and top-level design for testability (DFT).
- Be responsible for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.
- Be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
- Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
- Supervise and mentor other engineers