UST Title –

Who we are:

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

 

Summary:

UST is looking for SOC Design Verification – Project Lead.

 

Job Description

We are seeking a highly motivated and skilled SOC Verification Engineer to join our growing team. As a SOC Verification Engineer, you will be responsible for the verification of complex System-on-Chip (SOC) designs, ensuring their functionality, performance, and reliability. You will work closely with design and architecture teams to develop and execute verification plans, build testbenches, and debug failures. This role offers the opportunity to contribute to cutting-edge technology and make a significant impact on our product development.

 

Key Responsibilities

Develop and execute comprehensive verification plans for SOC designs. Create and maintain verification environments using industry-standard methodologies (UVM, OVM, VMM). Build testbenches, including stimulus generation, monitors, and scoreboards. Debug and analyze simulation failures to identify root causes. Collaborate with design and architecture teams to resolve design issues. Contribute to the improvement of verification methodologies and processes. Document verification results and provide regular progress updates. Participate in code reviews and provide constructive feedback.

 

Skills Required

Strong understanding of digital design principles and SOC architecture. Proficiency in hardware description languages (Verilog, SystemVerilog). Experience with verification methodologies (UVM, OVM, VMM). Experience with simulation tools (e.g., Cadence, Synopsys, Mentor Graphics). Strong debugging and problem-solving skills. Excellent communication and collaboration skills. Familiarity with scripting languages (e.g., Python, Perl).

 

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 12+ years of experience in SOC verification. Proven track record of successfully verifying complex digital designs. Experience with coverage-driven verification. Experience with formal verification is a plus.

 

 

What we believe:

We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do. 

Humility:

We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity:

Through business, we will better the lives of those less fortunate than ourselves.

Integrity:

We honour our commitments and act with responsibility in all our relationships.

 

Equal Employment Opportunity Statement

 

UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.

 

All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

 

• To support and promote the values of UST.

• Comply with all Company policies and procedures