**Minimum qualifications:** + Bachelor’s degree in Electrical Engineering or equivalent practical experience. + 4 years of experience with physical design. + Experience with System on a Chip (SoC) cycles. **Preferred qualifications:** + Master’s degree in Electrical Engineering. + Experience in coding with System Verilog and scripting with TCL. + Experience with layout verification and design rules. + Experience in VLSI design in SoC. + Experience with multiple-cycles of SoC in ASIC design. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing ASICs used to accelerate machine learning computation in Data centers. You will collaborate with members of architecture, verification, power and performance, physical design, and more to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power, and area in mind. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. **Responsibilities:** + Take ownership of one or more physical design partitions or top level. + Drive to the closure of timing and power consumption of the design. + Contribute to design methodology, libraries, and code review. + Define the physical design related rule sets for the functional design engineers. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.