We are looking for a synthesis engineer with 6+ years of experience and have minimum one year of experience in leading a team. 

JD:

• Experience of doing synthesis using fusion compiler.

• Experience on multi clock domain timing analysis and debugging working with cross functional teams

• Good knowledge about timing, area utilization, power and congestion concepts 

• Good knowledge of FEV and TCL scripting 

• Experience in scheduling the task and communicating with stakeholders