Bengaluru, Karnataka, India
19 hours ago
Senior Lead Engineer - RTL Design
Job Requirements

  Must have skills:

1.  Should have worked on ASIC/SOC projects using 22nm or smaller technology node

2.  Expertise in automated RTL Integration using any of the industry standard tool/EDA flow

3.  Good knowledge on AHB/AXI/APB/PIPE interface

4.  Expertise in Verilog RTL coding and debugging

5.  Expertise in writing ASIC UPF and synthesis constraints

6.  Expertise in Lint, CDC and VCLP, Synthesis, LEC

  Nice to have skills:

7.  Exposure to ARM/PCIe/Ucie/SPI/USB/I2C

8.  Exposure to Low power designs



Work Experience

  Must have skills:

1.  Should have worked on ASIC/SOC projects using 22nm or smaller technology node

2.  Expertise in automated RTL Integration using any of the industry standard tool/EDA flow

3.  Good knowledge on AHB/AXI/APB/PIPE interface

4.  Expertise in Verilog RTL coding and debugging

5.  Expertise in writing ASIC UPF and synthesis constraints

6.  Expertise in Lint, CDC and VCLP, Synthesis, LEC

  Nice to have skills:

7.  Exposure to ARM/PCIe/Ucie/SPI/USB/I2C

8.  Exposure to Low power designs



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