Job Requirements

Key Responsibilities:

Own and drive DFT architecture and implementation for analog mixed signal chips from concept to production.Develop scan insertion, scan compression, and at-speed test strategies to meet high fault coverage and test cost targets.Work with cross-functional teams including design, verification, and physical design to ensure DFT integration and tapeout readiness.Define and implement test strategies for analog and mixed-signal IPs, including DFT hooks, wrappers, and test mode integration.Create test patterns and perform ATPG analysis to ensure test coverage goals are met.Debug DFT-related issues during silicon bring-up and collaborate with product/test engineering teams.Automate and optimize DFT flows and scripting for scalability and efficiency.

Required Qualifications:

B.E./B.Tech or M.E./M.Tech in Electrical Engineering or related discipline.Minimum 10 years of hands-on experience in DFT with successful tapeouts.Strong knowledge of scan insertion, scan compression, transition fault (at-speed) testing, and boundary scan (IEEE 1149.1/1500).Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired.Experience with ATPG tools, test coverage analysis, and test pattern generation.Solid understanding of DFT for AMS blocks, including challenges in testability of analog circuits.Familiarity with scripting languages (TCL, Perl, Python) for automation.Good understanding of STA constraints for DFT and impact on synthesis and physical design.

Proven experience in silicon debug and production test support

Work Experience
Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired.Experience with ATPG tools, test coverage analysis, and test pattern generation.Solid understanding of DFT for AMS blocks, including challenges in testability of analog circuits.Familiarity with scripting languages (TCL, Perl, Python) for automation.Good understanding of STA constraints for DFT and impact on synthesis and physical design.