Job Requirements

Job Summary:

We are looking for a highly skilled and hands on Senior Lead Engineer to lead and drive SOC Design Verification for an ARM based SoC Design.

Extensive experience in SV/UVM based SOC or IP Verification.

 

Key Responsibilities:

Lead end-to-end DV activities : Testbench architecture, Test plan, Coding, execution and Sign-off.Strong knowledge in CPU based SOC architecture.Develop and execute System Verilog/UVM Testbenches for SOC/IP VerificationDevelop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random testsAnalyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution.Define Functional/Code/Assertion coverage metrics, sign-off checklist and drive to closure.Mentor & Drive Junior Team, conduct reviews and ensure quality.

Work Experience

Required Skills:

8+ years of hands-on experience in IP/SOC Verification with Strong SOC Architecture knowledgeProficiency in SV/UVM based testbench development and constrain random verification.Familiarity with standard verification tools ( VCS, Xcelium) and debug environmentScripting skills ( Python/Perl) Strong debugging, analytical and problem-solving skills Experience in two or more  High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)

Optional Preferred Skills

Exposure to Formal Verification or assertion-based verification.Power aware verification ( UPF)GLS & Xprop runs