Senior DV Engineer
QuEST Global
Job Requirements
Work Experience
Job Summary:
We are looking for passionate and motivated SoC Design Verification Engineers to work on CPU-based SoC and IP verification projects.
You will be part of a dynamic verification team contributing to pre-silicon verification using System Verilog & UVM
Key Responsibilities:
Develop and execute Systemverilog/UVM Testbenches for SOC/IP VerificationDevelop Test plan, Implement & run directed, random, and constrained random testsWrite C & SV/UVM based tests development & debugDebug simulation failures and work with RTL team for resolution.Functional & code coverage analysis and sign-off checklist closure.Work Experience
Required Skills:
4-8 years of Verification experience with hands-on knowledge in SV/UVMExperience in ARM based SOC & IP Level VerificationStrong working knowledge in CPU(ARM) based SOC and SOC integration conceptsFamiliarity with standard verification tools ( VCS, Xcelium) and debug environmentScripting skills ( Python/Perl) Strong debugging, analytical and problem-solving skills Experience in one of the High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)Optional/Preferred Skills
Exposure to Formal Verification or assertion-based verification.Power aware verification ( UPF)GLS & Xprop runs
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