Senior DFT Engineer
Amazon.com
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.
Work hard. Have fun. Make history.
We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production.
As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability — from early DFT architecture planning to high-volume silicon bring-up and yield ramp.
Key job responsibilities
Key job responsibilities
Lead development & implementation of DFT architecture including system level DFT for a full chip
Write and guide others in writing design flow and project documentation.
Own DFT planning, milestone tracking, and cross-functional checklist reviews.
Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists.
Review and sign-off SoC level DFT mode timing closure using static timing analysis
Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon
Keep informed on and introduce new technology into Design-for-Test process as appropriate.
Work hard. Have fun. Make history.
We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production.
As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability — from early DFT architecture planning to high-volume silicon bring-up and yield ramp.
Key job responsibilities
Key job responsibilities
Lead development & implementation of DFT architecture including system level DFT for a full chip
Write and guide others in writing design flow and project documentation.
Own DFT planning, milestone tracking, and cross-functional checklist reviews.
Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists.
Review and sign-off SoC level DFT mode timing closure using static timing analysis
Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon
Keep informed on and introduce new technology into Design-for-Test process as appropriate.
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