Test Plan Writing, Knowledgeable in UVM and System Verilog, Debugging RTL issues, Coverage Writing and SVA Waveform debug using Verdi. Must be proficient in IP Verification/SOC Verification. The ideal candidate for the Senior Design Verification Engineer position will have a strong background in ASIC/FPGA verification methodologies, experience with formal verification tools, and a proven track record of delivering high-quality verification results. In addition, the candidate should possess excellent communication skills, the ability to work effectively in a team environment, and a passion for solving complex technical challenges.