Meet the Team

Join Cisco’s CHG Team in Armenia, a leader in physical design and implementation for groundbreaking networking chips under the globally recognized Silicon One brand. Our team focuses on advancing chip-level implementation and analysis for innovative technologies, employing advanced methodologies and best-in-class tools to solve large-scale design challenges. As a part of this innovative team, you’ll lead and collaborate on the physical implementation and sign-off of high-complexity silicon, ensuring the performance, reliability, and quality of the technology that powers tomorrow’s connectivity. Together, we are redefining what’s possible in networking technology.

Your Impact

As a Physical Design Manager, you will play a key leadership role in Cisco’s Silicon One development, overseeing the full physical implementation process from RTL to GDSII and tape-out. You will drive the team responsible for block-level and full-chip design, ensuring that all aspects meet rigorous performance, area, and power requirements. In this role, you’ll collaborate cross-functionally with teams spanning frontend, IP, and tool vendors, both locally and globally, to deliver signoff-clean, next-generation networking chips. Beyond technical leadership, you’ll foster a culture of mentorship, learning, and innovation—enabling your team and yourself to grow and make a real-world impact.

What You'll Do

Lead the team responsible for full-chip and block-level physical implementation, from RTL to GDSII and tape-out.Oversee all aspects of the physical design process, including synthesis, place and route, timing closure, and sign-off. Ensure all designs meet performance, area, and power requirements, and that handoffs between teams are seamless and timely. Collaborate closely with cross-functional teams to align on implementation challenges and solutions. Provide technical leadership, mentorship, and support to team members, empowering their growth and success. Engage in strategic planning and contribute ideas to optimize physical design methodologies and workflows.

Minimum Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. 8+ years of experience in ASIC design and physical implementation, including verification. Deep expertise with deep submicron CMOS technologies. Extensive knowledge of the full design cycle from RTL to GDSII. Strong understanding of Static Timing Analysis, timing closure, and design constraints. Proven skills in block-level synthesis, place and route, and timing closure. Familiarity with industry-standard physical design and sign-off tools. Excellent verbal and written communication skills in English. Proven experience managing technical teams in a fast-paced environment.

Preferred Qualifications

Direct experience with EM/IR and ESD analysis, including debugging and solution development. Proficiency in scripting languages such as Tcl, Python, or Shell to improve design flow efficiency. Experience collaborating with global teams and vendor partners. Demonstrated ability to mentor team members and foster a collaborative environment.#WEARECISCO
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