– Responsible for the full physical design cycle from Synthesis to GDSII
– Perform tasks like Synthesis, floor-planning, placement, CTS, routing, and timing analysis
– Perform the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/ PV(LVS/ANT/DRC/DFM) /Low power check ... tape-out procedures
– Ensure the design meets performance, power, and area constraints
– Utilize Electronic Design Automation (EDA) tools for design, simulation, and verification
– Work closely with stakeholders like: Design team, constraint team, DFT team, DV team, IP team to ensure the physical layout meets design specifications
– Perform physical verifications such as layout versus schematic (LVS) and design rule checking (DRC)
– Conduct parasitic extraction and analysis to optimize the performance of the IC
– Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
– Optimize designs for power, area, and performance
– Stay up to date with the latest technology trends (7nm/5nm/3nm and beyond), industry standards, and EDA tools
– Conduct logic synthesis, floor planning, power and clock distribution, timing optimization, signal integrity and place and route
– Work closely with team members to resolve design and flow
Work Experience
– Proficient in written and verbal communication in English (Japanese is plus)
– Proven work experience as a Physical Design Engineer
– Experience with EDA tools like Synopsys (ICC2, FC, Formality, ICV, Redhawk, PrimeTime, Tweaker ...) /Cadence (Innovus, QRC, Tempus, Voltus.. ) /Siemens (Calibre)
– Understanding of Physical design flow (From Synthesis to GDS out)
– Experience in Synthesis, floorplanning, placement, CTS, routing, constraint debugging, and timing analysis
– Experience in the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/ PV(LVS/ANT/DRC/DFM) /Low power check ... tape-out procedures
– Strong problem-solving and analytical skills
– Knowledge of scripting languages such as Tcl, Perl or Python
– Excellent teamwork and communication abilities