Company:Qualcomm Semiconductor Limited

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

The Qualcomm Memory System/Technology Team in the Process & Package Solutions Group is seeking a highly motivated engineer to focus on 3D design PDK development, tape out execution, and EDA user support for advanced semiconductor design flows. This role will involve close collaboration with internal design teams and external foundry partners and tool vendors to ensure robust design enablement and smooth tape out processes for cutting-edge technologies.

Responsibilities

Develop, maintain, and validate Process Design Kits (PDKs) for 3D integration of advanced logic nodes and DRAM process node, ensuring accuracy and usability across design environments.

Drive tapeout readiness and execution, including layout verification, sign-off checks, and coordination with foundries.

Provide EDA tool support for design teams, focusing on Cadence and other industry-standard platforms for layout, schematic, and verification flows.

Optimize design methodologies for layout efficiency, DRC/LVS compliance, and manufacturability.

Collaborate with cross-functional teams including process and packaging engineers, SoC design teams, and foundry partners to resolve design challenges.

Troubleshoot and resolve issues related to EDA tools, PDK integration, and tapeout flows in a timely manner.

Contribute to continuous improvement of design enablement infrastructure and automation scripts for enhanced productivity.

Manage tapeout waiver requests, ensuring proper documentation and approval workflows.

Create and maintain tapeout checklists and documentation to standardize processes and improve quality.

Oversee foundry IP management, including tracking, integration, and compliance with licensing agreements.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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