Company:Qualcomm Atheros, Inc.

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

A Lead SOC Physical Design Engineer plays a crucial role in the development and implementation of products at Qualcomm.  This role requires strong knowledge and experience with physical design tools (like Cadence or Synopsys), semiconductor processes, timing closure, clock tree synthesis, power optimization, and physical verification methodologies. Additionally, communication skills and the ability to lead multi-geo PD team are essential for success in this role.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:

•   Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.

•   12+ years of ASIC Physical design, physical verification, validation, integration, or related work experience.
•    5+ years of experience with physical design tools.
•    5+ years of experience with scripting tools and programming languages.

•    5+ years of experience with physical design verification methods.

•    4+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).

Principal Duties and Responsibilities:

* Physical Design: Leading and executing the physical design process of complex semiconductor chips, ensuring adherence to design specifications and requirements.
* Floorplanning: Leading and driving the creation of chip floorplans, considering various factors like functionality, power, performance, area, and routing congestion to optimize the layout.
* Timing Closure: Ensuring that the chip meets timing requirements by optimizing clock tree synthesis, placement, and routing.
* Place and Route: Leading and driving the placement and routing of logic gates and interconnects, optimizing for performance, power, and area.
* Power Optimization: Implementing power-saving techniques and strategies to meet low-power design goals.
* Physical Verification: Leading and guiding the conduction of design rule checks (DRC) ,  layout versus schematic (LVS) checks , ERC and other miscellaneous checks to ensure the physical design meets manufacturing requirements.
* Power Integrity: Ensuring that the chip meets the strict constraints of IR drop, Electromigration, and ESD path resistance checks.
* Collaboration: Working closely with design teams, CAD engineers, program management, IT and other cross-functional teams to achieve project goals and resolve design challenges.
* Methodology Development: Leading the development and improvement of physical design and verification methodologies (including AI based), flows, and tools to enhance efficiency and quality of chip designs.
* Team Leadership: Providing technical expertise, leadership and support within the physical design team across multi-geos. Also mentoring and guiding junior PD engineers.

Level of Responsibility:

Technical leadership and expertise in Physical Design and verification of complex semiconductor chips.

•    Provides supervision/guidance to other team members.

•    Decision-making is significant in nature and highly impacts program or project success.

•    Requires verbal and written communication skills to convey complex information. May require strong negotiation, tact and influence with large groups or high-level constituents.

•    Has a great degree of influence over key organizational decisions (e.g., is consulted by senior leadership , or directly makes key decisions that will have substantial impact over the organization).

•    Tasks, often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits:

$203,300.00 - $304,900.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.