We are currently seeking a highly skilled Lead RTL Engineer with expertise in automated RTL Integration using industry standard tools/EDA flow. The ideal candidate will possess a strong background in SDC and UPF constraints development and checking, along with experience in timing violation debug/fix at the netlist level. Additionally, the successful candidate will demonstrate good knowledge of AHB/AXI/APB/PIPE interfaces and expertise in Lint, CDC, VCLP, Synthesis, and LEC. 
Proficiency in Python and TCL scripting is essential for this role. Nice to have skills include exposure to PCIe/Ucie. If you are a talented RTL Engineer interested in taking on a leadership role in a dynamic environment, we encourage you to apply.