latency, high-speed broadband connectivity to un-served and under-served communities around the world.

Come work at Amazon!

As a Lead ATE Test Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design and develop innovative Test software solutions for products developed for and deployed in Amazon Leo phased array antennas in LEO satellites and ground terminal products.

You’ll be responsible for defining and developing characterization/validation test methodology of mm-wave RFICs for Amazon Leo custom silicon. You will focus on building modular test solutions for use in high-volume production. You must be responsive, flexible and able to succeed within an open collaborative peer environment.

Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.



Key job responsibilities
- Implement and optimize RF, mixed signal, and high-speed interface test routines for high-volume manufacturing.
- Design, develop, and verify on-chip calibration techniques for analog and mixed-signal circuits, including implementation of calibration algorithms, validation of calibration accuracy across process/voltage/temperature (PVT) corners, and development of ATE test methodologies to ensure proper calibration functionality and performance optimization
- Develop and execute test strategies for on-chip one-time programmable (OTP) memory, including understanding of programming mechanisms, verification methodologies, and common challenges such as bit yield optimization, programming voltage margins, redundancy schemes, and post-programming reliability validation
- Collaborate with system architecture and design teams to define, implement, and validate on-chip test features including built-in self-test (BIST), scan chains, JTAG interfaces, and design-for-test (DFT) structures to enable comprehensive production test coverage and facilitate efficient debug and failure analysis
- Optimize ATE test time through parallel testing strategies, adaptive test algorithms, and intelligent test flow sequencing while maintaining rigorous data quality standards through statistical process control (SPC), outlier detection, and correlation analysis to ensure production test efficiency without compromising yield learning or product reliability