Individual contributor Lead engineer - RTL and SoC integration

Mandatory: RTL, Verilog, SoC Integration, Digital Design

Desiared: Basic synthesis/timing, Python scripting for automating task

Should have comfortable working knowledge of industry standard ASIC tools on Linux (& editors like Vim) and i. Good technikal knowledge to be able to execute tasks without much supervision and should be able to guide juniors in the team.