Lead Engineer - RTL
QuEST Global
Job Requirements
Microarchitecture, Module design and simulationParticipate in SoC specifications reviews and contribute to micro-architecture definitions.Digital design, implementation and integration – RTL Coding, Lint, CDC, and Synthesis.Develop design constraints and coordinate to debug both functional and DFT test issuesB.A./B.S. in engineering, engineering management, or engineering operations requiredBSc/BEng in Electrical or Electronic engineering, MS preferred5-7 years industry experience with BS working in digital or mixed signal IC designDigital design knowledge:Verilog codingRegister file designSerial interfacesInterconnect fabricsState machine architectureClock domain crossingScan and self-testSynthesis, Linting, STAAutomation scripting and design flowsVerification, including System Verilog knowledgeLow power design, Power intent specification and validation methodology.System knowledge:Battery management, charging, voltage regulation and ARM based Subsystems/SOCs.Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation,Lint, CDC/RDC and power intent checks.Familiarity with Cadence, Synopsis design toolsAbility to work as part of a team and with low levels of supervision
Work Experience
Digital design knowledge:Verilog codingRegister file designSerial interfacesInterconnect fabricsState machine architectureClock domain crossingScan and self-testSynthesis, Linting, STAAutomation scripting and design flowsVerification, including System Verilog knowledgeLow power design, Power intent specification and validation methodology.System knowledge:Battery management, charging, voltage regulation and ARM based Subsystems/SOCs.Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation,Lint, CDC/RDC and power intent checks.Familiarity with Cadence, Synopsis design toolsAbility to work as part of a team and with low levels of supervision
Microarchitecture, Module design and simulationParticipate in SoC specifications reviews and contribute to micro-architecture definitions.Digital design, implementation and integration – RTL Coding, Lint, CDC, and Synthesis.Develop design constraints and coordinate to debug both functional and DFT test issuesB.A./B.S. in engineering, engineering management, or engineering operations requiredBSc/BEng in Electrical or Electronic engineering, MS preferred5-7 years industry experience with BS working in digital or mixed signal IC designDigital design knowledge:Verilog codingRegister file designSerial interfacesInterconnect fabricsState machine architectureClock domain crossingScan and self-testSynthesis, Linting, STAAutomation scripting and design flowsVerification, including System Verilog knowledgeLow power design, Power intent specification and validation methodology.System knowledge:Battery management, charging, voltage regulation and ARM based Subsystems/SOCs.Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation,Lint, CDC/RDC and power intent checks.Familiarity with Cadence, Synopsis design toolsAbility to work as part of a team and with low levels of supervision
Good understanding of customer and market requirements
Work Experience
Digital design knowledge:Verilog codingRegister file designSerial interfacesInterconnect fabricsState machine architectureClock domain crossingScan and self-testSynthesis, Linting, STAAutomation scripting and design flowsVerification, including System Verilog knowledgeLow power design, Power intent specification and validation methodology.System knowledge:Battery management, charging, voltage regulation and ARM based Subsystems/SOCs.Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation,Lint, CDC/RDC and power intent checks.Familiarity with Cadence, Synopsis design toolsAbility to work as part of a team and with low levels of supervision
Good understanding of customer and market requirements
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