Lead DV Engineer
QuEST Global
Job Requirements
Develop and execute Systemverilog/UVM Testbenches for IP VerificationDevelop Test plan, Implement & run directed, random, and constrained random testsDebug simulation failures and work with RTL team for resolution.Functional & code coverage analysis and sign-off checklist closure
Work Experience
7 to 9 years of IP Verification experience with hands-on knowledge in SV/UVMExperience in one of the High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)Experience in Serdes IP Verification preferrableFamiliarity with standard verification tools ( VCS, Xcelium) and debug environmentScripting skills ( Python/Perl) Strong debugging, analytical and problem-solving skills
Develop and execute Systemverilog/UVM Testbenches for IP VerificationDevelop Test plan, Implement & run directed, random, and constrained random testsDebug simulation failures and work with RTL team for resolution.Functional & code coverage analysis and sign-off checklist closure
Work Experience
7 to 9 years of IP Verification experience with hands-on knowledge in SV/UVMExperience in one of the High-Speed Interface Verification ( PCIE/USB/Ethernet/DDR*)Experience in Serdes IP Verification preferrableFamiliarity with standard verification tools ( VCS, Xcelium) and debug environmentScripting skills ( Python/Perl) Strong debugging, analytical and problem-solving skills
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