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Role : Lead Design Engineer, Digital Physical Desing

ResponsibilitiesBlock level Netlist to GDS deliverySubsystem level floorplan, PnR and timing closureFCFP/FCI/FCT activities - Full Chip Floor planning, Full chip Integration, Full Chip timing Leading/Guiding a team of 2-3 EngineersRequired Skills5+ years of experience in PnR and STAHandson experience in RTL/Netlist to GDS delivery of blocksGood understanding of DFT stitching and clock tree strategiesStrong at density and congestion issues resolutionComplex blocks floorplan, PnR and STA such as DDRIP. PCIE IPCapable of doing PV and IREM fixes along with the timingExposure to any of 7/6nm, 5/4nm & 3/2nm technologiesTCL and PERL scripting knowledge and experience in writing the scriptsGood exposure to Cadence EDA tool set needed for PDOptional SkillsHandson experience in low power designsHandson experience on subsystem level activitiesFlat Chip or small hier chip FC activitiesComplex IP integration like DDR and PCIeExperience in guiding freshers/internsWe’re doing work that matters. Help us solve what others can’t.