**Minimum qualifications:** + Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern Generation (ATPG), gate level simulations and silicon debug, low power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred qualifications:** + Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field. + Experience with IJTAG Instrument Connectivity Language (ICL), Procedural Description Language (PDL) terminology, ICL extraction, ICL modeling with Siemens Tessent Tool. + Experience with Spyglass-DFT, DFT Scan constraints and evaluating Static Timing Analysis (STA) paths. + Experience with a scripting language such as Perl or Python. + Knowledge of high performance design DFT techniques like Streaming Scan Network (SSN), High-Bandwidth IJTAG. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) . **Responsibilities:** + Work on subsystem level Design for Testing (DFT) Scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains. + Write scripts to automate the DFT flow. + Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow. + Work with junior members of the DFT team to deliver overall deliverables for two or more subsystems in a System on a Chip (SoC). + Responsible for overall DFT execution right from architecture phase to design, front-end and back-end implementations, gate level simulations and post-silicon debug. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.