Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:
This is a I/O modeling and characterization lead position in Methodology, Flow and Design Kit team involved in defining methodologies, flows and in delivering design kit including behavioral models and timing models for I/Os, memories and standard cell libraries in state of art CMOS/FinFET technology nodes for Qualcomm's advanced mobile baseband, Auto, IOE/IOT & consumer products.
Job Responsibilities:
Architect and oversee the development of RTL models in Verilog for various IO configurations, ensuring scalability, reusability, and alignment with system-level requirements.Define and drive the verification strategy, including planning, execution, and sign-off for both behavioral and transistor-level implementations. Ensure comprehensive coverage and alignment with project milestones.Lead the adoption and integration of advanced verification methodologies, including SystemVerilog Assertions (SVA), power-aware verification, and formal verification techniques.Own and guide the debug process across IP and SoC levels, collaborating with cross-functional teams to resolve complex issues efficiently.Provide technical leadership in analog/mixed-signal simulation methodologies, and mentor team members in interpreting and correlating results.Demonstrate deep expertise in VLSI circuit design, with hands-on experience in SPICE simulations and commercial characterization tools. Drive best practices across the team.Review and guide the development of stimulus for timing and power characterization, ensuring alignment with I/O circuit architecture and performance targets.Ensure accurate modeling and interpretation of Liberty formats including NLDM, CCS, and LVF. Provide guidance on model generation and validation.Collaborate closely with internal stakeholders, including SoC teams, to gather requirements and deliver high-quality behavioral and timing models throughout the design lifecycle.Take ownership to ensure that the I/O models are successfully integrated and consumed in the RTL-to-GDSII flow.Provide guidance to the physical design and timing closure teams in closing timing involving I/Os. Familiarity to static timing analysis tools and flows is a must.Engage with EDA tool vendors to influence tool development and drive methodology improvements aligned with requirements of a cutting-edge technology nodes. Drive the tool evaluations and define specifications and requirements for I/O modeling and characterization, ensuring alignment with project goals and technology scaling.Lead the development of new methodologies and flows to support complex and scalable designs. Drive technical reviews, mentor junior engineers, and foster a culture of continuous improvement.Champion automation initiatives using scripting languages such as Python, Perl, or TCL to enhance productivity, consistency, and quality across the design and verification flows.Preferred Qualifications
Master’s degree or Bachelor’s degree in electrical engineering.7+ years of experience in IP characterization, modeling and design verification.5+ years of experience in RTL coding, Verilog and System Verilog Test benches, Design verification, IP characterization or related work experience.5+ years of experience in managing, leading and mentoring a team.5+ years of experience in tool evaluation, flow development with scripting tools and programming languages.Experience managing projects across different sites, building processes and coordinating release schedules.Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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Pay range and Other Compensation & Benefits:
$140,000.00 - $210,000.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.