Google welcomes people with disabilities. **Minimum qualifications:** + Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. + 8 years of experience with Serializer/Deserializer (SERDES) key sub-blocks design, such as transmitter, receiver, phase-locked loops, clock and data recovery circuit. + Experience with lab bring-up, silicon characterization, and debug of mixed-signal IPs. + Experience with CMOS design, layout and validation. **Preferred qualifications:** + Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. + Experience with highly scaled CMOS (FinFET) design, layout and validation, low power design techniques such as dynamic voltage or frequency scaling and creating behavioral models of analog circuits in SystemVerilog or VerilogA and analysis of system level tradeoffs. + Experience covering the full product lifecycle: specification, architecture, design, and productization of PHYs (Physical Layer Protocols). + Familiarity with high speed SERDES sub-blocks such as Transmitter, PLL, CTLE, DFE, Sense Amplifier and CDR. + Familiarity with high speed IO specifications like PCIE, MIPI CDPHY, UCIE and LPDDR. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. **Responsibilities:** + Collaborate with architects and cross-functional teams to define high speed I/O specification and components. + Study specifications, build models and analyze the budget for high speed I/O components. + Perform mixed-signal circuit design, simulation, and verification for critical high speed I/O components. This includes, but is not limited to: Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), Differential Line Drivers (TX), Receivers (RX), Clock and Data Recovery (CDR) circuits, bias generators, regulators, and I/O cells. + Collaborate with cross-functional teams, including digital design, layout, verification, and system integration to ensure robust circuit performance. + Participate in post-silicon validation, debug, and characterization efforts. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.