Company:Qualcomm Technologies, Inc.

Job Area:Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary:

This position centers on floor-planning expertise at both block and top levels for industry-leading graphics core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of GPU performance and efficiency. This role is open in either San Diego or Austin location.

Key responsibilities include:

Driving floorplan architecture and optimization in collaboration with RTL and architecture teams to maximize PPAEngaging in cross-functional collaboration with verification, timing, power, and packaging teams to ensure holistic design convergencePartnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiencyMaking strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets

The ideal candidate will have/demonstrate the following:

Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high frequency designsExperience with physical synthesis and implementation tools - Synopsys Fusion Compiler, ICC2 and Cadence Genus/InnovusMust have good knowledge of static timing analysis, reliability and power analysisStrong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designsAbility to think outside the box for innovative solutions to improve power and eliminate performance bottlenecksStrong understanding of GPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performanceSolid working knowledge of scripting skills including tcl, perl or pythonExcellent communication skills and collaborating in a team environment is a must

Preferred Skills:

Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closureClose interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocksHands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and AreaHands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageousPrior experience in flow and methodology development is an advantageExcellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designsAbility to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams

Minimum Qualifications:

Bachelor’s degree in Electrical/Computer Engineering8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top levelStrong background in VLSI design, physical implementation and scriptingStrong background and experience working with industry standard Synthesis and Place and Route tools including Signoff toolsHands on experience taping out designs in sub-micron technology node design < 10nmExpect strong self-motivation and time management skills

Preferred Qualifications:

Master’s degree in Electrical/Computer Engineering8+ years of direct top level floor-planning large and high frequency IP experienceIn depth end to end experience from RTL2GDS, taping out at least 6 complex designsDirect hands on experience with bus/pin/repeater planning for entire IP

Minimum Qualifications:

•    Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits:

$108,500.00 - $162,700.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.