Responsible for architecting, implementing, and verifying high-speed crypto architectures on ASICs and advanced FPGA platforms for secure communications applications.

Requirements

Bachelor’s degree in Electrical Engineering or equivalent, with minimum 4 years of relevant experience, OR Master’s degree with minimum 2 years of relevant experience

Active SECRET clearance

Proficient in VHDL design and FPGA flow with 5+ years of hands-on experience

Experience with ASIC/FPGA design and verification for high-performance communications or networking products

Strong experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware with architecture/system design tradeoffs

Hands-on design/debug experience with Ethernet and TCP/IP protocols

Experience with synthesis, static timing analysis (STA), and RTL quality checks (RDC, CDC, Lint, Formal)

Board-level debug and lab validation skills on Linux-based SoC evaluation boards

Responsibilities

Derive engineering specifications from system requirements and develop detailed architecture

Execute RTL and/or HLS (C++ to RTL) design, synthesis, and verification processes

Develop test plans and perform module-level verification and system integration

Conduct silicon/FPGA bring-up, characterization, and production ramp support

Perform lab debug and software-driven validation for FPGA/ASIC platforms

Support collateral creation for production releases

Preferred Skills

Experience with Xilinx MPSOC platforms including SDKs, BSPs, and PetaLinux OS

Experience with high-speed protocols including PCIe, TCP/IP, Ethernet (hands-on protocol-level work beyond IP instantiation)

Familiarity with Synopsys DC/Primetime/Synplify, Vivado, Mentor Questa (UVM, CDC, RDC, Lint), and Catapult HLS tools

Experience with High-Level Synthesis (Vivado HLS, Mentor Calypto)

Knowledge of SystemVerilog Assertions (SVA) and Universal Verification Methodology (UVM)

Background in Aerospace/Defense development

Experience with C++ (OOP) for embedded software integration

Project leadership experience including earned value management (EVM)

Pay Details: $90.00 to $140.00 per hour

Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.

Equal Opportunity Employer/Veterans/Disabled

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The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
The California Fair Chance ActLos Angeles City Fair Chance OrdinanceLos Angeles County Fair Chance Ordinance for EmployersSan Francisco Fair Chance Ordinance

Massachusetts Candidates Only: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.