Job Requirements
Lead end-to-end DV activities : Testbench architecture, Test plan, Coding, execution and Sign-off.Strong knowledge in CPU based SOC architecture.Develop and execute System Verilog/UVM Testbenches for SOC/IP VerificationDevelop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random testsAnalyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution.Define Functional/Code/Assertion coverage metrics and sign-off checklist and drive to closure.Mentor & Drive Junior Team, conduct reviews and ensure quality.

Work Experience
Expertise in sv-uvm and C based verification environment for SOCKnowledge of ARM core, AXI protocol, tarmac debug, basic assembly code.Debugging failures at SOC levelGLS debug and bringup expertiseGood to have Emulation debug, post silicon debug, system level test-case creationLanguage/Methodoglogy : C, SV,UVMGood to have python knowledgeExcellent communication skills and willing to work on fast pace environment.