Job Requirements
Develop and execute Systemverilog/UVM Testbenches for SOC/IP VerificationDevelop Test plan, Implement & run directed, random, and constrained random testsWrite C & SV/UVM based tests Debug simulation failures and work with RTL team for resolution.Functional & code coverage analysis and sign-off checklist closure.

Work Experience
Expertise in sv-uvm and C based verification environmentKnowledge of ARM core, AXI protocolExperience in porting IP level SV-UVM environment to SS levelDebugging failures at SS levelGLS debug and bringup expertiseGood to have Emulation debug, post silicon debug, system level test-case creationLanguage/Methodoglogy : C, SV,UVMGood to have python knowledgeExcellent communication skills and willing to work on fast pace environment.