The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.


Work hard. Have fun. Make history.

We are seeking a skilled and hands-on DFT Engineer (Level 5) to contribute to the Design-for-Test (DFT) implementation for SoCs. This role requires strong technical expertise in scan, MBIST, boundary scan, STA closure, and silicon readiness to support high-volume SoC products. You will work in a cross-functional team environment alongside RTL, physical design, and test engineering teams.

Why This Role?
As an L5 DFT Engineer, you will play a critical hands-on role in defining and implementing Design-for-Test (DFT) strategies for next-generation SoCs. This role offers you the opportunity to work at the heart of silicon development, collaborating with architects, RTL designers, physical design, and test engineering teams to ensure silicon is testable, and production-ready.

If you're a self-motivated engineer who thrives in technically challenging environments and is passionate about high-quality, high-coverage test solutions, this role is an ideal platform to balance of technical depth, collaboration, and impactful execution on real silicon products.


Key job responsibilities
Insert, and verify DFT logic and components in subsystem RTL netlists. Enhance and improve DFT implementation to achieve DFT coverage targets. Review sign-off level, timing closure using static timing analysis of DFT mode. Generate and sign off high-quality pre-silicon DFT patterns.