Position Summary

Role and Responsibilities

5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas:Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modesMBIST architecture planning, repair architectures, insertion, verificationAnalog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYsTiming closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD teamTiming GLS, debug of fails in simulationsPost silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failuresUnderstanding of JTAG operation and debug required. Understanding of iJTAG protocol desirableUnderstanding of functional test cases, IO testing, testing of ARM processor coresAbility to lead a team across all aspects of DFT, interact with RTL, physical design teams for DFT implementation, anticipate risks, plan project timelines and milestones

Skills and Qualifications

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