Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design
- Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL
- Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow
- Analyze timing report and suggest for the solution
- Skillful in gate-level simulations with and without timing annotations
- Diagnose and analyze data logs during silicon bring-up phase to finalize prototype patterns
- Be responsible for Innovative Hardware DFT for new silicon device models, bare die & stacked die- driving re-usable test and debug strategies
Work Experience
Strong knowledge and experience in doing DFT designStrong understanding of scan and compression (EDT) circuitryFriendly with Synopsys OCC for both stuck-at/transition modesStrong understanding of MBIST circuitry when joining ASIC group by Mentor documentsFamiliar with programming language: Shell, Perl, TclExperience in EDA DFT toolsGood scripting skills and the ability to design and debug with minimal oversight