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Role : Design Engineer 1, Digital Physical Desing

ResponsibilitiesBlock level Netlist to GDS deliverySubsystem level PnR and timing closureRequired Skills3+ years of experience in PnR and STAHandson experience in RTL/Netlist to GDS delivery of blocksGood exposure to Placement, CTS and Routing techniquesCapable of doing PV and IREM fixes along with timingGood exposure to Cadence EDA tool set needed for PDTCL and PERL scripting knowledge and experience in writing the scriptsOptional SkillsComplex blocks floorplan, PnR and STAComplex IP integration like DDR and PCIeHands on experience in low power designsGood understanding of DFT stitchingExposure to any of 7/6nm, 5/4nm & 3/2nm technologiesWe’re doing work that matters. Help us solve what others can’t.