Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Qualcomm is one of the fastest growing semiconductor organizations, making high-end chips with the most advanced technologies. To support its growing needs, we have a Custom Solutions Team for design and development (RTL to GDS) of various highspeed and low power IP’s (mini-macros) which are used across different sub-systems in SoC.
In this position, you will be an integral part of the team with the opportunity to experience the entire ASIC design flow. This position involves the design and development of best-in-class custom digital IP from RTL to GDS for optimizing SoC Power, Performance and Area (PPA). It includes the IP specification definition, RTL design, architecture and circuit design, physical implementation, verification and sign offs. Candidates with coding and flow support experience are preferred.
Job Responsibilities:
Use industry standard and internally developed tools and flows (Cadence, Innovus, HSPICE, Primetime etc) to execute architecture or circuit level design with defined specifications.Oversee the IP implementation by either PNR or RTL.Simulate and sign off design margin and PPA metrics.Generate and release IP collaterals (functional/DFT/timing models, LEF abstract, DEF, etc) for SoC consumption.Conduct design reviews and documentations.Flow and methodology enablement support.Close collaboration with different teams across various time zones.Skillset/Experience:
Strong background and exposure in one of the digital design areas:Experience of digital library architecture and circuit design, and simulation sign off (HSPICE), such as custom circuit, standard cell or SRAM.Experience of synthesis, physical design (Genus, Innovus or FusionCompiler) and STA timing closure.Knowledge of semiconductor device physics and behavior; understanding of advanced technology, such as FinFET, Gate All Around is a plus.Adaptive to non-standard design flow.Programming skill in python, perl, tcl, shell, skill, etc is a strong plus.Variation-aware design experience is a plus.Exposure to RTL, Synthesis, Formal & functional verification or DFT is a plus.Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
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Pay range and Other Compensation & Benefits:
$115,600.00 - $173,400.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.