Cellular PPAC (Power, Performance Area and Cost) Engineer **San Diego, California, United States** **Hardware** **Summary** Posted: **Aug 12, 2025** Role Number: **200616064-3543** Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. Do you excel at crafting elegant solutions to complex challenges? Do you naturally prioritize the significance of every detail? As a member of our Hardware Technologies group, you'll contribute to designing, optimizing, and manufacturing our next-generation, high-performance, power-efficient cellular chips and system-on-chips (SoC). Your role will be pivotal in ensuring that Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. By joining this group, you'll be responsible for developing and building the technology that powers Apple's devices. We invite you to join us in delivering the next groundbreaking Apple products! In this highly visible position as a key technical member of the Cellular Power Performance Area & Cost optimization team, you'll play a crucial role in improving the Power, Performance, Area, and Cost efficiency metrics of Apple Cellular silicon. Your responsibilities will include optimizing Design and Implementation methodologies for cellular chips to achieve best-in-class efficiency metrics across all PPA dimensions. You'll identify and drive improvement opportunities through custom/semi-custom flows, IP development, design technology co-optimization, and advanced analytics. With practical design knowledge, you'll help differentiate and streamline Apple's silicon engineering methods. **Description** As a PPAC Optimization Engineer, you'll optimize the design and implementation methodology for cellular chips across multiple focus areas including area efficiency, power optimization, and design technology co-optimization. Your primary responsibilities will involve optimizing Power, Performance, Area, and Cost efficiency metrics through various approaches: - Identify utilization bottlenecks in physical design and develop architectural, design, and implementation-level solutions to improve utilizations. - Develop and implement Vmin and power optimization methodologies - Perform design technology co-optimization analysis, including optimal voltage point analysis for performance/power curves and identification of scaling trends and bottlenecks in new technology nodes - Collaborate closely with technology and IP teams to enhance efficiency through custom and semi-custom IP development - Conduct in-depth analysis of Frontend and Backend databases, as well as post-silicon data, to identify critical issues and improve PPA - Work closely with silicon technology, front-end, physical design, CAD, and other teams to develop innovative solutions and implement them on test chips **Minimum Qualifications** + Minimum BS and 10+ years of relevant industry experience. + VLSI background with hands-on experience in RTL to GDSII flows. + Prior experience in doing Power, Performance, Area and Cost optimizations for SoCs. + Experience with SoC power flows & Vmin optimization. + Experience with Design Technology Co-optimization, identifying and solving scaling bottlenecks in new technology nodes. + Rapid prototyping and scripting of methodologies and test chip block implementation. **Preferred Qualifications** + Solid understanding of Physical Design challenges, proficiency with synthesis, place and route tools, and implementation exploration. + Experience with Metal stack optimizations. + Experience performing Early Tech node analysis to identify implementation bottlenecks. + Design Technology Co-optimization expertise. + Strong analytical skills and ability to identify and communicate high return on investment opportunities. + Ability to apply data science and ML analytics for Frontend and Backend databases, as well as post-silicon data, to identify trends & patterns and fine-tune implementation methodologies. **Pay & Benefits** At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.Learn more about Apple Benefits. (https://www.apple.com/careers/us/benefits.html) Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088\_EEOC\_KnowYourRights6.12ScreenRdr.pdf) . Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088\_EEOC\_KnowYourRights6.12ScreenRdr.pdf) . Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation. Apple participates in the E-Verify program in certain locations as required by law.Learn more about the E-Verify program (https://www.apple.com/jobs/pdf/EverifyPosterEnglish.pdf) . Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more . Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more . Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines applicable in your area. It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.