Bengaluru, IND
19 hours ago
ASIC Register-Transfer Level Design Engineer, Silicon
**Minimum qualifications:** + Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. + 4 years of experience with RTL Design Engineering. + Experience in designing SOCs with Silicon Success. **Preferred qualifications:** + Master's Degree in Electrical Engineering or Computer Science or equivalent practical experience. + Experience in Verilog or System Verilog language. + Experience in Static Timing Analysis (STA) closure, DV test-plan review and coverage analysis of the sub-system and chip level verification. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. **Responsibilities:** + Define the microarchitecture of complex IPs, Subsystems or SOCs and work with the team to deliver a quality, schedule compliant and Power Performance Area (PPA) optimized design. + Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process. + Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. + Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. + Work with key design collaterals such as Synopsys Design Constraints (SDC) and Unified Power Format (UPF). Work with stakeholders to negotiate the right collateral quality and identify solutions/workarounds. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.
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